The present invention relates generally to semiconductor chip designs, and more particularly to a method and system for checking errors with respect to an integration between a chip and package substrate layouts.
In conventional design methodologies, the design process and the chip manufacturing are done at different locations. Only at the final assembly process when all the individual components come together for assembly, any problems unnoticeable during the design phase may surface. Such problems include voltage supply differences, logic level incompatibilities and layout incompatibilities. If errors are not caught in the early stages, the production efficiency will be degraded.
Errors and design rule violations are often found at a chip packaging stage, due to inconsistencies between a chip layout and package substrate layout. The integration of package substrate and chip layouts has always been hard for chip designers, because in traditional chip fabrication processes, a package substrate layout has always been an untouchable territory for chip designers. Conventionally, connections between the package substrate and chip are only checked by a spreadsheet comparison, a process that could be very error-prone for most of the contents of the spreadsheet are manually keyed-in.
It is therefore desirable in the art of semiconductor chip design to provide an improved method and system for checking the integration of the chip and package substrate layouts for errors or design rule violations.